As high speed packet transmission schemes in IMT-2000 (International Mobile Telecommunication-2000), studies are being conducted for HSDPA (High Speed Downlink Packet Access) and HSUPA (High Speed Uplink Packet Access) that are directed to implementing increased peak transmission speed and high throughput, for example. Moreover, in addition to the above-described schemes, high speed packet transmission schemes directed to implementing further increased speed, are being conducted in 3GPP RAN LTE (Long term Evolution). In these high speed packet transmission schemes, the Hybrid-ARQ technique is necessary for improving throughput.
Hybrid-ARQ refers to a transmission method combining ARQ (Auto Repeat request) and FEC (Forward Error Correction), and is a technique of combining retransmission data and data that is received earlier and that nevertheless cannot be decoded, and performing error correction decoding. This makes it possible to improve SINR and coding gain enables decoding at smaller number of retransmissions than normal ARQ, and consequently, realizes improved received quality and efficient transmission.
The IR (Incremental Redundancy) scheme of this Hybrid-ARQ uses turbo code, is employed in HSDPA and HSUPA, and is likely to be adopted also in the 3GPP RAN LTE.
The IR scheme of Hybrid-ARQ is disclosed in Patent Document 1, and this scheme will be explained below using FIG. 1. In the IR scheme, as shown in FIG. 1, the transmitting side performs turbo coding and transmits information bits (hereinafter “systematic bits”) first in signals after turbo coding and the receiving side performs error detection. Upon detecting an error, the receiving side returns a NACK (Negative ACKnowlegement) signal to the transmitting side. In this case, the transmitting side transmits FEC parity bit 1 for error correction, and the receiving side performs turbo decoding using systematic bits and parity bit 1. When another error is detected, in response to a NACK signal from the receiving side, the transmitting side also transmits FEC parity bit 2 for error coding, and the receiving side performs turbo decoding using systematic bits and parity bits 1 and 2.
Patent Document 1: Japanese Patent Application Laid-Open No. 2003-018131